Priority is claimed to Japanese Patent Application Number JP2005-049005 filed on Feb. 24, 2005, the disclosure of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a semiconductor device capable of protecting a semiconductor element from an overvoltage.
2. Description of the Related Art
In conventional semiconductor devices, for example, an N-type epitaxial layer is deposited on a P-type semiconductor substrate for producing an N-channel type LDMOS transistor. In the epitaxial layer, a P-type diffusion region is formed as a back-gate region. In the P-type diffusion region, an N-type diffusion region is formed as a source region. In the epitaxial layer, another N-type diffusion region is formed as a drain region. In addition, an N-type buried region extending over the semiconductor substrate and the epitaxial layer is formed below the drain region. This structure is designed such that a breakdown voltage in a PN junction region formed by the buried region and the semiconductor substrate is lower than a source-drain breakdown voltage of the LDMOS transistor. According to this structure, even in the case of applying an overvoltage that would break the LDMOS transistor to a drain electrode, the PN junction region formed by the buried region and the semiconductor substrate is broken down. As a result, the LDMOS transistor can be prevented from being broken due to the overvoltage. This technology is described for instance in Published Japanese Patent Translations of PCT International Publications for Patent Applications No. 10-506503 (page 4 to 5, and 7, FIGS. 1 and 2).
As mentioned above, in the conventional semiconductor device, the N-type buried region is formed below the drain region for preventing the LDMOS transistor from being broken due to the overvoltage applied to the drain region. The N-type buried region is formed so as to have a substantially equal to that of the drain region. According to this structure, when overvoltage is applied to the drain region to cause a breakdown of the PN junction region between the N-type buried region and the P-type semiconductor substrate, a breakdown current concentrates on the PN junction region. Therefore, there has been a problem that the PN junction region would be broken due to current a concentration and a heat generation resulting from the current concentration.
Further, in the conventional semiconductor device, in order to prevent the current concentration on the PN junction region, it is possible to counter this problem by forming the N-type buried region over a wider region. The conventional semiconductor device aims at improving a withstand voltage characteristic by use of a known RESURF principle. For this reason, the N-type buried region extends largely toward an isolation regionside. Meanwhile, a structure is adopted, in which the N-type buried region is additionally to the LDMOS transistor in order to form the PN junction region. That is, when the N-type buried region is formed over a wider region, a distance between the drain region and the isolation region increases, and an inactive region where no element is formed is widened. For this reason, there has been a problem that an element formation region cannot be efficiently arranged in terms of a chip size.